Computer systems typically use direct access storage devices (DASDs) for at least part of their memory storage. DASDs may include for example, a head-disk assembly (HDA) which comprises a hard disk and an actuator arm on which resides an inductive write head for writing to the hard disk. An actuator electronics (AE) module, which also typically resides on the actuator arm, provides the electrical current required by the inductive write head to write to the hard disk. The AE module is often implemented in integrated circuit chip form containing on-chip write driver circuitry. The write driver circuitry facilitates write operations by forcing current though the inductive write heads on the actuator arm.
As the performance of memory devices for computer systems increases, so too does the requirement for advanced driver circuits. A schematic diagram representing a typical write driver circuit 10 for providing current to a write head 12 is shown in FIG. 1. The portion of the figure representing the inductive write head 12 is enclosed in dashed lines near the center of the Figure. The write driver circuit 10 switches current to the inductive write head 12 and comprises current sources J2 and J5; resistors R0, R1, R6 and R7; and npn-type transistors Q0, Q5, Q10, Q13, Q24 and Q25. V.sub.cc provides a voltage supply for the circuit, and is typically on the order of five VDC (volts DC). V.sub.in0 and V.sub.in1 are differential voltage input signals which switch current through the inductive write head 12 in opposite directions, depending on whether V.sub.in0 is greater or less than V.sub.in1. The current for the inductive write head 12 is provided across two switching outputs 14 and 16 of the circuit 10, located at the emitters of transistors Q10 and Q13, respectively.
The inductive write head comprises head inductors L0-L2, capacitor C2, and resistor R8. Capacitors C3 and C4 represent inherent capacitances introduced by the wire connecting the inductive write head 12 and the write driver circuit 10 on the actuator armt which are typically separated by a couple of inches on the arm. Because the capacitances C3 and C4 are connected at one end to the inductive write head 12 and at the other end to ground, the inductive write head is completely floating (in terms of electrical potential) between the switching outputs of the driver circuitry at the output terminals 14 and 16 of the driver circuit 10.
The circuit of FIG. 1 operates in the following manner. If the voltage differential V.sub.in0 -V.sub.in1 is positive, that is, V.sub.in0 is greater than V.sub.in1, the current from current source J2 turns on transistor Q0 and the current from current source J5 flows through transistor Q24. Current flows from V.sub.cc through transistor Q13, and through the inductive write head 12 from switch output 16 to switch output 14. The current continues through transistor Q0 and down to current source J2. The current through transistor Q0 is on the order of 50 milliamps.
The current provided by current source J5 is a smaller current than that provided by current source J2 and causes a voltage drop across R6 which keeps transistor Q10 off. Ideally, as long as Q10 remains completely off, all of the current provided to the collector of transistor Q0 is provided by transistor Q13 through the inductive write head 12, and no portion of the total current provided to the collector of Q0 is supplied by Q10. However, the circuit 10 does not operate ideally because, during switching transients when the direction of current through the inductive write head changes, the voltage at the emitter of Q10 is variable. If at some point during the switching transient the voltage at the emitter of Q10 drops 0.7 volts below its base voltage, Q10 will be turned on. If Q10 is turned on, it will supply a portion of the current to the collector of Q0 in addition to that already provided by Q13, thereby causing distortion in the output current waveform through the write head 12. This distortion is manifested as a discontinuity in the head current waveform as it passes through zero current midway through the switching transient.
If the voltage differential V.sub.in0 -V.sub.in1 is negative, that is, V.sub.in0 is less than V.sub.in1, the current from current source J2 turns on transistor Q5 and the current from current source J5 flows through transistor Q25. The current through Q5 flows from V.sub.cc through Q10, and through the inductive write head 12 from switch output 14 to switch output 16. The current continues through Q5 and down to current source J2. The smaller current provided by current source J5 provides a voltage drop across R7 which keeps Q13 off. Ideally, as long as Q13 remains completely off, all of the current provided to the collector of Q5 is provided by Q10 through the inductive write head 12, and no portion of the total current provided to the collector of Q5 is supplied by Q13. During the switching transient, however, the voltage at the emitter of Q13 is variable and if at some point during this switching transient the voltage at the emitter drops 0.7 volts below its base voltage, Q13 will be turned on. Q13 will then supply a portion of the current to the collector of Q5, thereby causing a discontinuity, or distortion, in the output current waveform through the write head 12.
Changing the polarity of the input voltage differential between V.sub.in0 and V.sub.in1, then, causes the direction of the current through the inductive current head 12 to change, and results in distortion in the resulting inductor current waveform midway through the switching transient. The same type of distortion in the current output waveform may also occur if either of the transistors Q0 or Q5 go into saturation while turning on. In such a case, the resulting distortion in the output current waveform at the emitters of Q10 and Q13 is likely to exceed the limits which manufacturers place on pulse width variations in the inductive write head current waveform.
One manner of correcting for the discontinuity in the current output waveform experienced during the switching transients is to ensure that the emitters of transistors Q13 and Q10 are provided with a voltage swing sufficient to prevent (i) both of the transistors from turning on during the transient and (ii) saturation of the primary conducting transistor during the transient. In order to provide such a voltage swing, either a higher voltage supply V.sub.cc may be used or a reverse bias may be supplied to the base of Q10 (when the voltage differential V.sub.in0 -V.sub.in1 goes positive) or to the base of Q13 (when the voltage differential V.sub.in0 -V.sub.in1 goes negative). However, if a reverse bias voltage is provided, it will remain across the emitter-base junction of Q10 and Q13, respectively, even after the switching transient is complete, and may increase the potential for emitter-base breakdown during normal operation of the switch circuitry. The emitter-base breakdown typically occurs when the maximum reverse bias base voltage coincides with the highest positive voltage swing at the emitter of Q10 (or Q13). Emitter-base breakdown also presents a problem when higher voltage supplies are utilized, because higher supply voltages tend to accelerate emitter-base breakdown of switching transistors. If, for example, V.sub.cc is designed to provide +10 or +12 VDC instead of +5 VDC, this higher voltage will likely exceed the junction breakdown limit of the bipolar npn transistors used in the circuit of FIG. 1.
Thus it is an object of the present invention to provide an improved low distortion memory write current head driver which minimizes discontinuities in the driver output current, while utilizing a standard +12 VDC supply voltage, without increasing the potential for junction breakdown of switching transistors in the driver circuitry. It is a further object of the invention to provide such a current head driver which is capable of switching up to 120 milliamps of current in less than 5 nanoseconds.